Invention Grant
- Patent Title: Junction-less insulated gate current limiter device
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Application No.: US14454435Application Date: 2014-08-07
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Publication No.: US09679890B2Publication Date: 2017-06-13
- Inventor: Tirthajyoti Sarkar , Adrian Mikolajczak , Ihsiu Ho , Ashok Challa
- Applicant: Fairchild Semiconductor Corporation
- Applicant Address: US CA San Jose
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Agency: Brake Hughes Bellermann LLP
- Main IPC: H02H9/00
- IPC: H02H9/00 ; H01L27/02 ; H01L29/40 ; H01L29/772 ; H01L29/8605 ; H01L29/861 ; H01L29/66 ; H01L29/16 ; H01L29/20

Abstract:
In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.
Public/Granted literature
- US20150043114A1 JUNCTION-LESS INSULATED GATE CURRENT LIMITER DEVICE Public/Granted day:2015-02-12
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