Invention Grant
- Patent Title: Semiconductor device with suppressed two-step on phenomenon
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Application No.: US15157987Application Date: 2016-05-18
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Publication No.: US09679997B2Publication Date: 2017-06-13
- Inventor: Akitaka Soeno
- Applicant: Toyota Jidosha Kabushiki Kaisha
- Applicant Address: JP Toyota-shi
- Assignee: Toyota Jidosha Kabushiki Kaisha
- Current Assignee: Toyota Jidosha Kabushiki Kaisha
- Current Assignee Address: JP Toyota-shi
- Agency: Dinsmore & Shohl LLP
- Priority: JP2015-112904 20150603
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L29/739 ; H01L29/10 ; H01L29/06 ; H01L29/08 ; H01L29/861 ; H01L29/36

Abstract:
A semiconductor device includes an IGBT region with a bottom-body region on a front surface side of an IGBT drift region, an IGBT barrier region on a front surface side of the bottom-body region, and a top-body region on a front surface side of the IGBT barrier region. A diode region is include with a bottom-anode region on a front surface side of the diode drift region, a diode barrier region on a front surface side of the bottom-anode region, a top-anode region on a front surface side of the diode barrier region, and a pillar region extending from the front surface of the semiconductor substrate, piercing the top-anode region, and reaching the diode barrier region, and connected to the front surface electrode and the diode barrier region. An impurity concentration of the top-body region is lower than an impurity concentration of the bottom-anode region.
Public/Granted literature
- US20160359027A1 SEMICONDUCTOR DEVICE Public/Granted day:2016-12-08
Information query
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