One or more processors group a plurality of timing arcs into a plurality of equivalence classes. Each timing arc includes one or more delay tables. One or more processors generate, for at least one equivalence class of the plurality of equivalence classes, an average sensitivity to a condition by performing a weighted average on respective sensitivities of timing arcs to the condition. One or more processors determine a sensitivity of an electronic circuit to the condition based, at least in part, a match between one or more attributes of the electronic circuit and one or more attributes present in the at least one equivalence class.