Invention Grant
- Patent Title: Circuit for generating a sense amplifier enable signal with variable timing
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Application No.: US15132388Application Date: 2016-04-19
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Publication No.: US09685209B1Publication Date: 2017-06-20
- Inventor: Kedar Janardan Dhori , Vinay Kumar , Ashish Kumar
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Gardere Wynne Sewell LLP
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/12 ; G11C7/14 ; G11C7/06

Abstract:
A sense amplifier enable signal generating circuit includes an input coupled to a dummy bit line of a memory. A voltage comparator circuit compares a voltage on the dummy bit line to a threshold voltage and generates an output signal when the voltage falls below that threshold voltage. A multi-bit counter circuit counts a count value in response to the output signal. A pull-up circuit pulls up the voltage on the dummy bit line in response to the output signal. A count comparator circuit compares the count value to a count threshold and generates a sense amplifier enable signal when the count value equals the count threshold.
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