Invention Grant
- Patent Title: Method for reducing loss of silicon cap layer over SiGe source/drain in a CMOS device
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Application No.: US15222624Application Date: 2016-07-28
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Publication No.: US09685382B1Publication Date: 2017-06-20
- Inventor: Jialei Liu
- Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
- Applicant Address: CN Shanghai CN Beijing
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee Address: CN Shanghai CN Beijing
- Agency: Kilpatrick Townsend and Stockton LLP
- Priority: CN201510939766 20151215
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/08 ; H01L29/161 ; H01L29/165 ; H01L29/78
Abstract:
A method for forming a semiconductor device includes providing a semiconductor substrate including a PMOS region and an NMOS region. A spacer material layer is deposited. Then, a first photo masking and etch process is used to form first sidewall spacers on the sidewalls of the gate structures in the NMOS region. A sacrificial surface layer is formed. Next, a second photo masking and etch process is used to form second sidewall spacers on the sidewalls of the gate structures in the PMOS region. After the second photoresist layer is removed, with the sacrificial layer masking the NMOS region, stress layers are formed in source/drain regions in the PMOS region, and a cover layer is formed on the stress layers. The method further includes removing the sacrificial material layer, the first sidewall spacers, and the second sidewall spacer.
Public/Granted literature
- US20170170074A1 METHOD FOR REDUCING LOSS OF SILICON CAP LAYER OVER SIGE SOURCE/DRAIN IN A CMOS DEVICE Public/Granted day:2017-06-15
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