Invention Grant
- Patent Title: Performance enhanced semiconductor socket
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Application No.: US14565724Application Date: 2014-12-10
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Publication No.: US09689897B2Publication Date: 2017-06-27
- Inventor: James Rathburn
- Applicant: HSIO TECHNOLOGIES, LLC
- Applicant Address: US MN Maple Grove
- Assignee: HSIO Technologies, LLC
- Current Assignee: HSIO Technologies, LLC
- Current Assignee Address: US MN Maple Grove
- Main IPC: G01R1/04
- IPC: G01R1/04

Abstract:
A test socket for IC devices includes a multi-layered socket housing with at least one center layer and first and second surface layers. The first and second surface layers have a thickness and dielectric constant less than that of the center layers. A plurality of contact members are located in center openings in the center layer with distal ends extending into openings in the first and second layers. The distal ends of the contact members having at least one dimension greater than the openings in the first and second surface layers to retain the contact members in the socket housing. The contact members include center portions with major diameters less than the diameters of the center openings, such that an air gap is maintained between the contact members and the center layer.
Public/Granted literature
- US20150091600A1 PERFORMANCE ENHANCED SEMICONDUCTOR SOCKET Public/Granted day:2015-04-02
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