A linear stacked stage suitable for REBL may include a first upper fast stage configured to translate a first plurality of wafers in a first direction along a first axis, the first upper fast stage configured to secure a first plurality of wafers; a second upper fast stage configured to translate a second plurality of wafers in a second direction along the first axis, the second upper fast stage configured to secure the second plurality of wafers, the second direction opposite to the first direction, wherein the translation of the first upper fast stage and the translation of the second upper fast stage are configured to substantially eliminate inertial reaction forces generated by motion of the first upper fast stage and the second upper fast stage; and a carrier stage configured to translate the first and second upper fast stages along a second axis.