Invention Grant
- Patent Title: Method to pattern <10 micrometer conducting and passivating features on 3D substrates for implantable devices
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Application No.: US14213733Application Date: 2014-03-14
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Publication No.: US09694190B2Publication Date: 2017-07-04
- Inventor: Vanessa Tolosa , Satinderpall S. Pannu , Heeral Sheth , Angela C. Tooker , Kedar G. Shah , Sarah H. Felix
- Applicant: Lawrence Livermore National Security, LLC
- Applicant Address: US CA Livermore
- Assignee: Lawrence Livermore National Security, LLC
- Current Assignee: Lawrence Livermore National Security, LLC
- Current Assignee Address: US CA Livermore
- Agent Eddie E. Scott
- Main IPC: A61N1/05
- IPC: A61N1/05 ; A61N1/375 ; H05K3/02 ; H05K3/28
Abstract:
An implantable device has a cylindrical base, at least one electrode on the cylindrical base, at least one electrically conducting lead on the cylindrical base connected to the electrode wherein the electrically conducting lead has a feature size of
Public/Granted literature
Information query
