An upgrade is performed for a complex programmable logical device (CPLD), the method comprising: splitting a serial vector format (SVF) file into a first SVF sub-file and a second SVF sub-file; generating a first Versa Module Europa (VME) bus file according to the first SVF sub-file; generating a second VME bus file according to the second SVF sub-file; and backing up register information and a pin signal of the CPLD. The method further comprises upgrading a program of the CPLD using the first SVF sub-file and the first VME bus file. The method further comprises using the second SVF sub-file and the second VME bus file to release the pin of the CPLD after the register information and the pin signal of the CPLD are restored by the first SVF sub-file and the first VME bus file.