Invention Grant
- Patent Title: Instructions and logic to vectorize conditional loops
-
Application No.: US15344836Application Date: 2016-11-07
-
Publication No.: US09696993B2Publication Date: 2017-07-04
- Inventor: Tal Uliel , Elmoustapha Ould-Ahmed-Vall , Bret L. Toll
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F15/76
- IPC: G06F15/76 ; G06F9/30 ; G06F15/80

Abstract:
A processing device to provide vectorization of conditional loops includes vector physical registers to store a source vector having a first plurality of n data fields, and a destination vector comprising a second plurality of data fields corresponding to the first plurality of data fields, wherein each of the second plurality of data fields corresponds to a mask value in a vector conditions mask. The processing device includes a decode stage to decode a first processor instruction specifying a vector expand operation and a data partition size, and execution units to set elements of the source vector to n count values, obtain a decisions vector, generate the vector conditions mask according to the decisions vector, and copy data from consecutive vector elements in the source vector, into unmasked vector elements of the destination vector, without copying data from the source vector into masked vector elements of the destination vector.
Public/Granted literature
- US20170052785A1 INSTRUCTIONS AND LOGIC TO VECTORIZE CONDITIONAL LOOPS Public/Granted day:2017-02-23
Information query