Invention Grant
- Patent Title: Semiconductor storage device and test method thereof using a common bit line
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Application No.: US15337139Application Date: 2016-10-28
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Publication No.: US09697911B2Publication Date: 2017-07-04
- Inventor: Makoto Yabuuchi
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Koutou-ku, Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Koutou-ku, Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2013-194249 20130919
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C29/12 ; G11C8/08 ; G11C7/12 ; H01L27/11

Abstract:
Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.
Public/Granted literature
- US20170047129A1 SEMICONDUCTOR STORAGE DEVICE AND TEST METHOD THEREOF USING A COMMON BIT LINE Public/Granted day:2017-02-16
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