The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes providing a substrate having a first conductive feature in a first dielectric material layer; selectively etching the first conductive feature, thereby forming a recessed trench on the first conductive feature; forming an etch stop layer on the first dielectric material layer, on the first conductive feature and sidewalls of the recessed trench; forming a second dielectric material layer on the etch stop layer; forming an opening in the second dielectric material layer; and forming a second conductive feature in the opening of the second dielectric material layer. The second conductive feature is electrically connected with the first conductive feature.