Invention Grant
- Patent Title: Methods of forming 3-D circuits with integrated passive devices
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Application No.: US14977214Application Date: 2015-12-21
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Publication No.: US09698131B2Publication Date: 2017-07-04
- Inventor: Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Haynes and Boone, LLP
- Main IPC: H01L25/16
- IPC: H01L25/16 ; H01L21/683 ; H01L21/768 ; H01L23/48 ; H01L23/00 ; H01L25/065 ; H01L25/00 ; H01L49/02 ; H01L23/538 ; H01L23/58 ; H01L27/06 ; H01L23/367 ; H01L27/02

Abstract:
Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.
Public/Granted literature
- US20160111404A1 METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES Public/Granted day:2016-04-21
Information query
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