Invention Grant
- Patent Title: Vertical NAND and method of making thereof using sequential stack etching and self-aligned landing pad
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Application No.: US15080269Application Date: 2016-03-24
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Publication No.: US09698153B2Publication Date: 2017-07-04
- Inventor: Jin Liu , Yanli Zhang , Murshed Chowdhury , Raghuveer S. Makala , Johann Alsmeier
- Applicant: SANDISK TECHNOLOGIES INC.
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L27/00
- IPC: H01L27/00 ; H01L27/1157 ; H01L27/11582 ; H01L21/28 ; H01L21/822 ; H01L27/11551 ; H01L27/06 ; H01L27/11524 ; H01L27/11578 ; H01L29/66 ; H01L29/788 ; H01L29/792 ; H01L27/11556

Abstract:
Alignment between memory openings through multiple tier structures can be facilitated employing a temporary landing pad. The temporary landing pad can have a greater area than the horizontal cross-sectional area of a first memory opening through a first tier structure including a first alternating stack of first insulating layers and first spacer material layers. An upper portion of a first memory film is removed, and a sidewall of an insulating cap layer that defines the first memory opening can be laterally recessed to form a recessed cavity. A sacrificial fill material is deposited in the recessed cavity to form a sacrificial fill material portion, which functions as the temporary landing pad for a second memory opening that is subsequently formed through a second tier structure including second insulating layers and second spacer material layers. A memory stack structure can be formed through the first and second tier structures.
Public/Granted literature
- US20160204117A1 VERTICAL NAND AND METHOD OF MAKING THEREOF USING SEQUENTIAL STACK ETCHING AND SELF-ALIGNED LANDING PAD Public/Granted day:2016-07-14
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