An improved FinFET has a gate structure on only a portion of the available surface on a fin, thereby providing a FinFET with a finer granularity width dimension. To form the FinFET, a first etch-resistant sacrificial layer and a second etch-resistant spacer layer are formed on the fin. The spacer layer is etched anisotropically to remove the spacer layer from the top and upper sidewalls of the fin while leaving the spacer layer on the lower sidewalls of the FinFET. A gate dielectric and conducting layer are then deposited and shaped to form a structure that is effective as a gate only on the top and upper sidewalls of the fin.