Invention Grant
- Patent Title: System and method for clock generation with an output fractional frequency divider
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Application No.: US14660711Application Date: 2015-03-17
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Publication No.: US09698800B2Publication Date: 2017-07-04
- Inventor: Jan-Michael Stevenson
- Applicant: Linear Technology Corporation
- Applicant Address: US CA Milpitas
- Assignee: Linear Technology Corporation
- Current Assignee: Linear Technology Corporation
- Current Assignee Address: US CA Milpitas
- Agency: VLP Law Group LLP
- Agent Edward Kwok
- Main IPC: H03L7/16
- IPC: H03L7/16 ; H03K21/10 ; H03K23/48
Abstract:
A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).
Public/Granted literature
- US20160036455A1 SYSTEM AND METHOD FOR CLOCK GENERATION WITH AN OUTPUT FRACTIONAL FREQUENCY DIVIDER Public/Granted day:2016-02-04
Information query
