Invention Grant
- Patent Title: Controller, semiconductor memory system and operating method thereof
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Application No.: US14743914Application Date: 2015-06-18
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Publication No.: US09698827B2Publication Date: 2017-07-04
- Inventor: Jae-Bum Kim
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2015-0025192 20150223
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/15 ; G06F11/10 ; G11C29/52 ; H03M13/11 ; G11C16/26 ; G11C11/56 ; G11C29/04 ; H03M13/23 ; H03M13/25 ; H03M13/29

Abstract:
An operating method of a controller that includes: when a first ECC decoding on data read from a semiconductor memory device according to a hard read voltage fails, generating one or more quantization intervals based on the number of unsatisfied syndrome check (USC), which is a result of the first ECC decoding; and performing a second ECC decoding on the data by generating soft read data according to soft read voltages determined by the hard read voltage and the quantization intervals.
Public/Granted literature
- US20160246673A1 CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF Public/Granted day:2016-08-25
Information query
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