Controller, semiconductor memory system and operating method thereof
Abstract:
An operating method of a controller that includes: when a first ECC decoding on data read from a semiconductor memory device according to a hard read voltage fails, generating one or more quantization intervals based on the number of unsatisfied syndrome check (USC), which is a result of the first ECC decoding; and performing a second ECC decoding on the data by generating soft read data according to soft read voltages determined by the hard read voltage and the quantization intervals.
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