Circuits, devices, methods for decision feedback equalization are described. A decision feedback circuit can include a plurality of decision feedback equalizer (DFE) branches, each DFE branch including: a pre-computation stage for generating a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; and a decision feedback stage including a multiplexer circuit for selecting at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches. For at least a first DFE branch of the plurality of DFE branches, at least one selection line for the multiplexer circuit in the decision feedback stage of at least the first DFE branch of the plurality of DFE branches is an intermediate value from a multiplexer circuit for a second DFE branch of the plurality of DFE branches.