Invention Grant
- Patent Title: Test pattern generation device, fault detection system, test pattern generation method, program and recording medium
-
Application No.: US14371317Application Date: 2013-01-09
-
Publication No.: US09702927B2Publication Date: 2017-07-11
- Inventor: Yasuo Sato , Seiji Kajihara
- Applicant: Kyushu Institute of Technology
- Applicant Address: JP Saitama
- Assignee: Japan Science and Technology Agency
- Current Assignee: Japan Science and Technology Agency
- Current Assignee Address: JP Saitama
- Agency: Rankin, Hill & Clark LLP
- Priority: JP2012-002214 20120110
- International Application: PCT/JP2013/050150 WO 20130109
- International Announcement: WO2013/105564 WO 20130718
- Main IPC: G01R27/28
- IPC: G01R27/28 ; G01R31/00 ; G01R31/14 ; G01R31/28 ; G01R31/3183 ; G01R31/319

Abstract:
A test pattern generation device for generating a new test pattern keeping the feature of original test patterns. The test pattern generation device includes a logic value generation unit for generating a new logic value by referring given logic values of a first bit, a second bit and a third bit and by keeping or reversing a logic value of the second bit, wherein a logic value of the first bit is the same with a logic value of a given initial test pattern or a new test pattern generated by the test pattern generation device based on the initial test pattern, wherein a logic value of the second bit is the same with a logic value of the initial test pattern, and wherein a logic value of the third bit is the same with a logic value of the initial test pattern or the new test pattern.
Public/Granted literature
Information query