Invention Grant
- Patent Title: Method of controlling etch-pattern density and device made using such method
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Application No.: US14814703Application Date: 2015-07-31
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Publication No.: US09704765B2Publication Date: 2017-07-11
- Inventor: Peter N. Manos, II
- Applicant: Polar Semiconductor, LLC
- Applicant Address: US MN Bloomington
- Assignee: Polar Semiconductor, LLC
- Current Assignee: Polar Semiconductor, LLC
- Current Assignee Address: US MN Bloomington
- Agency: Kinney & Lange, P.A.
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L21/66 ; H01L29/78 ; H01L29/04 ; H01L29/16 ; H01L21/02 ; H01L21/3065 ; H01L21/308 ; H01L21/265 ; H01L21/306 ; H01L29/66
Abstract:
A method of controlling an etch-pattern density of a polysilicon layer includes depositing polysilicon on a wafer. The method includes determining polysilicon-etch regions that include DMOS source regions within circuit-device areas of the wafer. The method includes calculating an etch area of the polysilicon-etch regions and then comparing the calculated etch area of the polysilicon-etch regions to a predetermined minimum etch area. If the calculated etch area is less than a predetermined threshold, the method adds polysilicon-etch regions within non-circuit-device areas to the determined polysilicon-etch regions within the circuit-device areas until the comparing step results in the calculated etch area of the polysilicon-etch regions being greater than the predetermined minimum etch area. The method includes etching the polysilicon from the polysilicon-etch regions in both the circuit-device areas and the non-circuit-device areas. Adding polysilicon-etch regions in non-circuit device areas can advantageously facilitate automatic process control of an etch step.
Public/Granted literature
- US20170033022A1 METHOD OF CONTROLLING ETCH-PATTERN DENSITY AND DEVICE MADE USING SUCH METHOD Public/Granted day:2017-02-02
Information query
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