Invention Grant
- Patent Title: Three dimensional integrated circuit
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Application No.: US14993015Application Date: 2016-01-11
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Publication No.: US09704835B2Publication Date: 2017-07-11
- Inventor: Theodore E. Fong , Michael I. Current
- Applicant: Silicon Genesis Corporation
- Applicant Address: US CA Santa Clara
- Assignee: SILICON GENESIS CORPORATION
- Current Assignee: SILICON GENESIS CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L21/822
- IPC: H01L21/822 ; H01L25/10 ; H01L21/762 ; H01L25/00 ; H01L27/06

Abstract:
A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.
Public/Granted literature
- US20160204088A1 THREE DIMENSIONAL INTEGRATED CIRCUIT Public/Granted day:2016-07-14
Information query
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