Invention Grant
- Patent Title: VDMOS having shielding gate electrodes in trenches and method of making the same
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Application No.: US15181186Application Date: 2016-06-13
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Publication No.: US09704986B2Publication Date: 2017-07-11
- Inventor: Mau Lam Lai , Yeuk Yin Mong , Duc Quang Chau
- Applicant: International Onizuka Electronics Limited
- Applicant Address: HK Hong Kong
- Assignee: International Onizuka Electronics Limited
- Current Assignee: International Onizuka Electronics Limited
- Current Assignee Address: HK Hong Kong
- Agency: Wayne & King LLC
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/08 ; H01L29/10 ; H01L29/40 ; H01L29/423 ; H01L29/66 ; H01L29/417

Abstract:
A VDMOS includes a substrate; an epitaxial layer; first and second trenches defined in the epitaxial layer; a shielding gate and a control gate formed in the trenches; a body region formed at the epitaxial layer and between the first and second trenches; a N+ source region formed at the body region; a distinct doping region formed in the epitaxial layer underneath the body region, extending towards bottoms of the trenches; a channel defined between the N+ source region and epitaxial layer adjacent to the trenches; an insulating layer defining a contact hole extending into the body region and the first trench; a P+ body pickup region formed in the body region corresponding to the contact hole; and a metal layer haying a butting contact filled in the contact hole, connecting the N+ source region, P+ body pickup region, and control gate and/or shielding gate in the first trench.
Public/Granted literature
- US20170104095A1 VDMOS AND METHOD FOR MAKING THE SAME Public/Granted day:2017-04-13
Information query
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