There is provided a reconfigurable semiconductor device including a plurality of logic units connected to each other using an address line or a data line, each logic unit including a plurality of address lines, a plurality of data lines, a clock signal line configured to receive a system clock signal, a delay element configured to delay the system clock signal, a memory cell unit configured to operate in synchronization with a clock signal, and an address decoder configured to decode an address signal to output the decoded signal to the memory cell unit. The logic unit configuring a combination logic circuit operates in synchronization with a delayed clock signal outputted from the delay element.