A target apparatus 2 for debug includes a processing pipeline 18 for executing a sequence of program instructions. A debug interface 26 receives debug command signals corresponding directly or indirectly to debug program instructions to be executed. An instruction buffer 24 stores both the debug program instructions and non-debug program instructions. An arbiter 30 selects between both the debug program instructions and the non-debug program instructions stored within the instruction buffer to form the sequence of program instructions to be executed by the processing pipeline. A complex coherent memory system 4, 6, 8, 10, 12, 14, 32 is shared by the debug program instructions and the non-debug program instructions such that they obtain the same coherent view of memory.