Translation entry invalidation in a multithreaded data processing system
Abstract:
In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is removed and buffered in sidecar logic. While the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request. Subsequent memory referent instructions are ordered with respect to the broadcast synchronization request by a synchronization instruction.
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