Invention Grant
- Patent Title: Double patterning method
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Application No.: US14935792Application Date: 2015-11-09
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Publication No.: US09711372B2Publication Date: 2017-07-18
- Inventor: Chia-Ying Lee , Jyu-Horng Shieh
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L21/311 ; H01L21/768 ; H01L21/033 ; H01L21/027

Abstract:
In some embodiments, the disclosure relates to a method of forming an integrated circuit device. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions. A mandrel is formed over the first mask layer and the cut regions, and the first mask layer is etched using the mandrel form a patterned first mask. The substrate is etched according to the patterned first mask and the cut regions to form trenches in the substrate, and the trenches are filled with conductive metal to form conductive lines.
Public/Granted literature
- US20160064248A1 DOUBLE PATTERNING METHOD Public/Granted day:2016-03-03
Information query
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