Invention Grant
- Patent Title: Bump structural designs to minimize package defects
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Application No.: US14879710Application Date: 2015-10-09
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Publication No.: US09711475B2Publication Date: 2017-07-18
- Inventor: Jing-Cheng Lin , Cheng-Lin Huang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/498 ; H01L21/56 ; H01L23/31

Abstract:
A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.
Public/Granted literature
- US20160035687A1 BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS Public/Granted day:2016-02-04
Information query
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