Invention Grant
- Patent Title: Electrostatic discharge clamp circuit for ultra-low power applications
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Application No.: US14491017Application Date: 2014-09-19
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Publication No.: US09716381B2Publication Date: 2017-07-25
- Inventor: Yen-po Chen , Yoonmyung Lee , Jae-Yoon Sim , Massimo Alioto , Dennis Sylvester , David Blaauw
- Applicant: The Regents of The University of Michigan
- Applicant Address: US MI Ann Arbor
- Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
- Current Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
- Current Assignee Address: US MI Ann Arbor
- Agency: Harness, Dickey & Pierce, P.L.C.
- Main IPC: H02H9/04
- IPC: H02H9/04 ; H02H1/04

Abstract:
An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.
Public/Granted literature
- US20150085406A1 Electrostatic Discharge Clamp Circuit For Ultra-Low Power Applications Public/Granted day:2015-03-26
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