Invention Grant
- Patent Title: Method of fabricating a semiconductor package
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Application No.: US14044122Application Date: 2013-10-02
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Publication No.: US09720013B2Publication Date: 2017-08-01
- Inventor: Pin-Cheng Huang , Yi-Che Lai
- Applicant: Siliconware Precision Industries Co., Ltd.
- Applicant Address: TW Taichung
- Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee Address: TW Taichung
- Agency: Mintz Levin Cohn Ferris Glovsky and Popeo, P.C.
- Agent Peter F. Corless; Steven M. Jensen
- Priority: TW101139428A 20121025
- Main IPC: G01R31/26
- IPC: G01R31/26 ; G01R1/04 ; G01R31/28

Abstract:
A method of testing a semiconductor structure is provided, including providing at least a semiconductor structure having an interposer and a semiconductor element disposed on the interposer; disposing the semiconductor structure on a carrier having a supporting portion, with the interposer being supported by the supporting portion; and performing a test process. The semiconductor structure has been tested for its electrical performance prior to packaging, thereby eliminating the necessity for a conductive pathway to pass through an inner circuit of an package substrate. Therefore, the testing process is accelerated and the time is save.
Public/Granted literature
- US20140118019A1 METHOD OF TESTING A SEMICONDUCTOR STRUCTURE Public/Granted day:2014-05-01
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