- Patent Title: Automatic loop vectorization using hardware transactional memory
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Application No.: US14222040Application Date: 2014-03-21
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Publication No.: US09720667B2Publication Date: 2017-08-01
- Inventor: Sara S. Baghsorkhi , Albert Hartono , Youfeng Wu , Nalini Vasudevan , Cheng Wang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: G06F9/45
- IPC: G06F9/45

Abstract:
Technologies for automatic loop vectorization include a computing device with an optimizing compiler. During an optimization pass, the compiler identifies a loop and generates a transactional code segment including a vectorized implementation of the loop body including one or more vector memory read instructions capable of generating an exception. The compiler also generates a non-transactional fallback code segment including a scalar implementation of the loop body that is executed in response to an exception generated within the transactional code segment. The compiler may detect whether the loop contains a memory read dependent on a condition that may be updated in a previous iteration or whether the loop contains a potential data dependence between two iterations. The compiler may generate a dynamic check for an actual data dependence and an explicit transactional abort instruction to be executed when an actual data dependence exists. Other embodiments are described and claimed.
Public/Granted literature
- US20150268940A1 AUTOMATIC LOOP VECTORIZATION USING HARDWARE TRANSACTIONAL MEMORY Public/Granted day:2015-09-24
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