Invention Grant
- Patent Title: Least recently used (LRU) cache replacement implementation using a FIFO storing indications of whether a way of the cache was most recently accessed
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Application No.: US13943958Application Date: 2013-07-17
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Publication No.: US09720847B2Publication Date: 2017-08-01
- Inventor: Thang Q. Nguyen , John D. Coddington , Sanjay R. Deshpande
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, INC.
- Current Assignee: NXP USA, INC.
- Current Assignee Address: US TX Austin
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/122 ; G06F12/0891 ; G06F12/123 ; G06F12/127 ; G06F12/128 ; G06F7/78
Abstract:
A method and apparatus for calculating a victim way that is always the least recently used way. More specifically, in an m-set, n-way set associative cache, each way in a cache set comprises a valid bit that indicates that the way contains valid data. The valid bit is set when a way is written and cleared upon being invalidated, e.g., via a snoop address, The cache system comprises a cache LRU circuit which comprises an LRU logic unit associated with each cache set. The LRU logic unit comprises a FIFO of n-depth (in certain embodiments, the depth corresponds to the number of ways in the cache) and m-width. The FIFO performs push, pop and collapse functions. Each entry in the FIFO contains the encoded way number that was last accessed.
Public/Granted literature
- US20150026410A1 LEAST RECENTLY USED (LRU) CACHE REPLACEMENT IMPLEMENTATION USING A FIFO Public/Granted day:2015-01-22
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