Invention Grant
- Patent Title: Processing system with interspersed processors with multi-layer interconnection
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Application No.: US15219095Application Date: 2016-07-25
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Publication No.: US09720867B2Publication Date: 2017-08-01
- Inventor: Carl S. Dobbs , Michael R. Trocino , Michael B. Solka
- Applicant: Coherent Logix, Incorporated
- Applicant Address: US TX Austin
- Assignee: COHERENT LOGIX, INCORPORATED
- Current Assignee: COHERENT LOGIX, INCORPORATED
- Current Assignee Address: US TX Austin
- Agency: Meyertons Hood Kivlin Kowert & Goetzel, P.C.
- Agent Jeffrey C. Hood; Brian E. Moore
- Main IPC: G06F15/76
- IPC: G06F15/76 ; G06F15/00 ; G06F13/40 ; G06F13/28 ; G06F13/16 ; G06F9/445 ; G06F13/42

Abstract:
Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
Public/Granted literature
- US20160335218A1 Processing System With Interspersed Processors With Multi-Layer Interconnection Public/Granted day:2016-11-17
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