One embodiment provides a method of building a wire resistance corner model for an interconnect metal level in a semiconductor device. The method comprises determining nominal on-wafer widths and wire thicknesses at minimum and maximum design widths of the interconnect metal level, and determining standard deviations for global variations in on-wafer width and wire thickness. The method further comprises determining maximum and minimum statistical corner values for interconnect wire resistance. A first corner solution that minimizes a maximum absolute difference between a model corner value and a statistical corner value of the maximum statistical corner values is computed. A second corner solution that minimizes a maximum absolute difference between a model corner value and a statistical corner value of the minimum statistical corner values is computed.