Invention Grant
- Patent Title: Hybrid integration fabrication of nanowire gate-all-around GE PFET and polygonal III-V PFET CMOS device
-
Application No.: US15157421Application Date: 2016-05-18
-
Publication No.: US09721846B1Publication Date: 2017-08-01
- Inventor: Deyuan Xiao
- Applicant: Zing Semiconductor Corporation
- Applicant Address: CN Shanghai
- Assignee: ZING SEMICONDUCTOR CORPORATION
- Current Assignee: ZING SEMICONDUCTOR CORPORATION
- Current Assignee Address: CN Shanghai
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: CN201610150107 20160316
- Main IPC: H01L21/283
- IPC: H01L21/283 ; H01L29/66 ; H01L21/8238 ; H01L29/06 ; H01L29/423 ; H01L29/49 ; H01L29/51 ; H01L29/786 ; H01L27/092 ; H01L27/12 ; H01L21/84
Abstract:
The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the PMOS the first nanowire is formed with high hole mobility and in the active region of the NMOS the second nanowire is formed with high electron mobility to achieve the objective of improving the performance of nanowire semiconductor device.
Information query
IPC分类:
