Invention Grant
- Patent Title: Semiconductor package and its manufacturing method
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Application No.: US15364851Application Date: 2016-11-30
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Publication No.: US09721900B2Publication Date: 2017-08-01
- Inventor: Naoki Hayashi
- Applicant: J-Devices Corporation
- Applicant Address: JP Usuki
- Assignee: J-Devices Corporation
- Current Assignee: J-Devices Corporation
- Current Assignee Address: JP Usuki
- Agency: TYPHA IP LLC
- Priority: JP2015-241986 20151211
- Main IPC: H01L23/28
- IPC: H01L23/28 ; H01L21/48 ; H01L23/538 ; H01L23/00 ; H01L21/768 ; H01L21/683

Abstract:
Provided is a bonding method to construct a bonding with high thermal reliability between electrodes formed on both chip surfaces of a semiconductor device and wiring. The bonding method includes: bonding a semiconductor chip over a first substrate with a bonding film interposed therebetween; forming a first insulating film over the semiconductor chip; forming a first via in the first insulating film; forming a first wiring over the first insulating film so as to be electrically connected to the semiconductor chip through the first via; forming a second via in the bonding film; and forming a second wiring under the semiconductor chip so as to be electrically connected to the semiconductor chip through the second via.
Public/Granted literature
- US20170170123A1 SEMICONDUCTOR PACKAGE AND ITS MANUFACTURING METHOD Public/Granted day:2017-06-15
Information query
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