Invention Grant
- Patent Title: Low parasitic capacitor array
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Application No.: US15136368Application Date: 2016-04-22
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Publication No.: US09722622B2Publication Date: 2017-08-01
- Inventor: Gehesh Edakkuttathil Muhammed , Naveen KV , Arun Mohan , Shagun Dusad
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Priority: IN2107/CHE/2015 20150424
- Main IPC: H03M1/12
- IPC: H03M1/12 ; H01L23/522 ; H01L27/08 ; H01G4/30 ; H03M1/80 ; H01G4/38 ; H01L49/02

Abstract:
The disclosure provides a capacitor array. The capacitor array includes one or more first metal plates vertically stacked parallel to each other. A second metal plate is horizontally stacked to couple one end of each first metal plate of the one or more first metal plates. One or more third metal plates are vertically stacked parallel to the one or more first metal plates. Each third metal plate of the one or more third metal plates is stacked between two first metal plates.
Public/Granted literature
- US20160315630A1 LOW PARASITIC CAPACITOR ARRAY Public/Granted day:2016-10-27
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