A semiconductor device includes an analog-digital converter circuit. The analog-digital converter circuit includes a delay cell array that includes n-number (n is a natural number of 2 or more) of serially-coupled delay cells, receives a reference clock signal, and utilizes an analog input signal as the power supply voltage for delay cells in each stage, and an encoder that encodes the output signal of the delay cells in each stage of the delay cell array. The n number of delay cells include a delay quantity weighted for each delay cell, and the encoder encodes the output signal of the delay cell in each stage of the delay cell array by weighting corresponding to the number of delay cell stages. The delay cells output signal without changing polarity of inputted signals.