Invention Grant
- Patent Title: Method of fabricating semiconductor structure using planarization process and cleaning process
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Application No.: US15012821Application Date: 2016-02-01
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Publication No.: US09748111B2Publication Date: 2017-08-29
- Inventor: Yi-Liang Ye , Kuang-Hsiu Chen , Chueh-Yang Liu , Yu-Ren Wang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: H01L21/461
- IPC: H01L21/461 ; H01L21/321 ; H01L29/66 ; H01L21/3205 ; H01L21/283 ; H01L21/02 ; H01L21/3105

Abstract:
A method for fabricating a semiconductor structure includes following steps. First, a first layer, a second layer and a third layer are sequentially formed on the substrate. The second layer is conformally disposed on the top surface of the first layer. The second layer and the first layer have different compositions, and the third layer and the second layer also have different compositions. Then, a planarizing process is performed on the third layer until portions of the second layer are exposed. Afterwards, hydrofluoric acid and aqueous oxidant are concurrently or sequentially provided to the remaining second and third layers. Finally, an etch back process is carried out to remove all the second layer and portions of the first layer.
Public/Granted literature
- US20170221723A1 METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE USING PLANARIZATION PROCESS AND CLEANING PROCESS Public/Granted day:2017-08-03
Information query
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