Invention Grant
- Patent Title: Method for forming through silicon via in N+ epitaxy wafers with reduced parasitic capacitance
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Application No.: US14632531Application Date: 2015-02-26
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Publication No.: US09748114B2Publication Date: 2017-08-29
- Inventor: Kangguo Cheng , Subramanian S. Iyer , Pranita Kerber , Ali Khakifirooz
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Steven Meyers
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48 ; H01L21/768 ; H01L23/48 ; H01L23/538 ; H01L21/265 ; H01L21/266 ; H01L21/268 ; H01L21/324 ; H01L29/36

Abstract:
A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.
Public/Granted literature
- US20150179548A1 THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE Public/Granted day:2015-06-25
Information query
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