Invention Grant
- Patent Title: Chip to wafer package with top electrodes and method of forming
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Application No.: US14590891Application Date: 2015-01-06
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Publication No.: US09748162B2Publication Date: 2017-08-29
- Inventor: Zhiqi Wang , Junjie Li , Ying Yang , Qiong Yu , Wei Wang
- Applicant: China Wafer Level CSP Co., Ltd.
- Applicant Address: CN Suzhou, Jiangsu
- Assignee: China Wafer Level CSP Co., Ltd.
- Current Assignee: China Wafer Level CSP Co., Ltd.
- Current Assignee Address: CN Suzhou, Jiangsu
- Agency: Wolf, Greenfield & Sacks, P.C.
- Priority: CN201410018025 20140116
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/07 ; H01L23/00 ; H01L25/00 ; H01L21/768 ; H01L23/31 ; H01L25/065

Abstract:
A chip package and a method for forming the same are provided. The method includes: providing a first chip, wherein the first chip comprises a first surface and a second surface, and a first plurality of pads are disposed on the first surface; providing a second chip, wherein the second chip comprises a third surface and a fourth surface, a second plurality of pads are disposed on the third surface; combining the second surface of the first chip and the third surface of the second chip, wherein the second plurality of pads are out of the combination area of the first chip and the second chip; and forming a first insulation layer, wherein the first insulation layer covers the first chip, and is combined with the second chip. Processes of the method are simple, and the chip package is small.
Public/Granted literature
- US20150200153A1 CHIP PACKAGE AND METHOD FOR FORMING THE SAME Public/Granted day:2015-07-16
Information query
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