A memory structure is provided. The memory structure includes a first chip. The first chip has an array region and a periphery region. The first chip includes a first stack and a plurality of through structures. The first stack is disposed in the periphery region. The first stack includes alternately stacked conductive layers and insulating layers. The through structures each include an opening, a dielectric layer and a channel material. The opening is through the first stack. The dielectric layer is disposed on a sidewall of the opening. The channel material is disposed in the opening, and the channel material covers the dielectric layer.