Invention Grant
- Patent Title: Wafer structure and method for wafer dicing
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Application No.: US14577141Application Date: 2014-12-19
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Publication No.: US09748187B2Publication Date: 2017-08-29
- Inventor: Yueh-Chuan Lee , Chia-Chan Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/00 ; H01L23/58 ; H01L21/78 ; H01L21/306

Abstract:
The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed on a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top surface of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top surface layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the wafer substrate is exposed.
Public/Granted literature
- US20160181213A1 WAFER STRUCTURE AND METHOD FOR WAFER DICING Public/Granted day:2016-06-23
Information query
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