Invention Grant
- Patent Title: NMOS regulated voltage reference
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Application No.: US14795836Application Date: 2015-07-09
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Publication No.: US09753481B2Publication Date: 2017-09-05
- Inventor: R. Jacob Baker , Ward Parkinson
- Applicant: HGST, Inc.
- Applicant Address: US CA San Jose
- Assignee: HGST, INC.
- Current Assignee: HGST, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson & Sheridan, LLP
- Main IPC: G05F3/16
- IPC: G05F3/16 ; G05F3/26

Abstract:
A method and system for generating a reference voltage are disclosed. The reference voltage is generated by generating a voltage VRIGHT using a first transistor and generating a voltage VBIAS using a second transistor. The gates of the two transistors are connected to a common node VREF, but the loads of the transistors have different resistances. At least one differential pair is used to detect a difference between voltages VRIGHT and VBIAS. VREF is forced to a value at which the source-drain currents in each of the transistors is equal. The transistors sued are NMOS transistors.
Public/Granted literature
- US20160124456A1 NMOS REGULATED VOLTAGE REFERENCE Public/Granted day:2016-05-05
Information query
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