- Patent Title: Method, apparatus, and system for energy efficiency and energy conservation including determining an optimal power state of the apparatus based on residency time of non-core domains in a power saving state
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Application No.: US14603955Application Date: 2015-01-23
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Publication No.: US09753531B2Publication Date: 2017-09-05
- Inventor: Sanjeev S. Jahagirdar , Ryan Wells , Inder Sodhi
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F13/24
Abstract:
A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.
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