Invention Grant
- Patent Title: Multiplier pipelining optimization with a postponed estimation correction
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Application No.: US14668349Application Date: 2015-03-25
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Publication No.: US09753692B2Publication Date: 2017-09-05
- Inventor: T. J. O'Dwyer , Pierre Laurent
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Grossman, Tucker, Perreault & Pfleger, PLLC
- Main IPC: G06F7/38
- IPC: G06F7/38 ; G06F7/523

Abstract:
One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
Public/Granted literature
- US20160283195A1 MULTIPLIER PIPELINING OPTIMIZATION WITH A POSTPONED ESTIMATION CORRECTION Public/Granted day:2016-09-29
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