Invention Grant
- Patent Title: Topology-aware processor scheduling
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Application No.: US14793234Application Date: 2015-07-07
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Publication No.: US09753780B2Publication Date: 2017-09-05
- Inventor: Mohammed Abouzour , John Smirnios
- Applicant: SYBASE, INC.
- Applicant Address: US CA Dublin
- Assignee: SYBASE, INC.
- Current Assignee: SYBASE, INC.
- Current Assignee Address: US CA Dublin
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F9/46
- IPC: G06F9/46 ; G06F9/50 ; G06F9/48

Abstract:
In an example embodiment, a method of operating a task scheduler for one or more processors is provided. A topology of one or more processors is obtained, the topology indicating a plurality of execution units and physical resources associated with each of the plurality of execution units. A task to be performed by the one or more processors is received. Then a plurality of available execution units from the plurality of execution units is identified. An optimal execution unit is then determined, from the plurality of execution units, to which to assign the task, based on the topology. The task is then assigned to the optimal execution unit, after which the task is sent to the optimal execution unit for execution.
Public/Granted literature
- US20170010920A1 TOPOLOGY-AWARE PROCESSOR SCHEDULING Public/Granted day:2017-01-12
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