Invention Grant
- Patent Title: Implementing signal integrity fail recovery and mainline calibration for DRAM
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Application No.: US15293645Application Date: 2016-10-14
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Publication No.: US09753806B1Publication Date: 2017-09-05
- Inventor: Stephen P. Glancy , Jeremy R. Neaton , Anuwat Saetow , Jacob D. Sloat
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Joan Pennington
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G06F11/14 ; G11C29/52

Abstract:
A method, system and memory controller are provided for implementing signal integrity fail recovery and mainline calibration for Dynamic Random Access Memory (DRAM). After identifying a failed DRAM, the DRAM is marked as bad and taken out of mainline operation. Characterization tests and periodic calibrations are run to evaluate optimal settings and to determine if the marked DRAM is recoverable. If recoverable, the marked DRAM chip is redeployed. If unrecoverable, error reporting is provided to the user.
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