Invention Grant
- Patent Title: Method for process variation analysis of an integrated circuit
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Application No.: US14818349Application Date: 2015-08-05
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Publication No.: US09753895B2Publication Date: 2017-09-05
- Inventor: Chin-Cheng Kuo , Kmin Hsu , Wei-Yi Hu , Wei Min Chan , Jui-Feng Kuan
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F17/18

Abstract:
A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.
Public/Granted literature
- US20150339414A1 METHOD FOR PROCESS VARIATION ANALYSIS OF AN INTEGRATED CIRCUIT Public/Granted day:2015-11-26
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