Invention Grant
- Patent Title: Determining slack estimates for multiple instances of a cell in a hierarchical circuit design
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Application No.: US14885920Application Date: 2015-10-16
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Publication No.: US09754069B2Publication Date: 2017-09-05
- Inventor: Qiuyang Wu , Chang Zhao
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Embodiments perform static timing analysis using a digital representation of a circuit. The digital representation of the circuit includes multiple instances of a cell in a hierarchical cell block circuit. Timing context information is determined for each instance of the cell included in the circuit. A merged timing context information is determined to bound and cover each of the plurality of instances of the cell. A slack estimate is determined for a pair of ports for each instance of the cell. The instance with the smallest slack estimate is identified. A slack estimate for a pair of ports of the cell is determined based on the merged timing information of the cell. A timing credit is determined for the pair of ports based on the slack of the instance with the smallest slack and the slack estimate from the bound information for the pair of ports.
Public/Granted literature
- US20170109468A1 DETERMINING SLACK ESTIMATES FOR MULTIPLE INSTANCES OF A CELL IN A HIERARCHICAL CIRCUIT DESIGN Public/Granted day:2017-04-20
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