Invention Grant
- Patent Title: Method and device for compact eFuse array
-
Application No.: US15336365Application Date: 2016-10-27
-
Publication No.: US09754680B2Publication Date: 2017-09-05
- Inventor: Chia Chi Yang
- Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Applicant Address: CN Beijing CN Shanghai
- Assignee: Semiconductor Manufacturing International (Beijing) Corporation,Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Beijing) Corporation,Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Beijing CN Shanghai
- Agency: Kilpatrick Townsend and Stockton
- Priority: CN201510731242 20151102
- Main IPC: G11C17/16
- IPC: G11C17/16 ; G11C17/18

Abstract:
An electrical fuse (eFuse) array includes eFuse cells arranged in multiple rows and columns. Each eFuse cell has an eFuse, a first diode, and a second diode coupled to an internal node, each eFuse cell further having first, second, and third terminals coupled, respectively, to the first diode, the second diode, and the eFuse. The eFuse array further includes a shared NMOSFET for each of the multiple rows, with a drain coupled to the third terminal of each of the plurality of eFuse cells in that row and a gate coupled to a word line. Each column includes a write bit line coupled to the second terminal of each of the eFuse cells in that column, and a read bit line coupled to the first terminal of the eFuse cell.
Public/Granted literature
- US20170125120A1 METHOD AND DEVICE FOR COMPACT eFuse ARRAY Public/Granted day:2017-05-04
Information query